1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having an output circuit that controls an impedance match and outputs an internal data,
2. Description of the Prior Art
Various semiconductor devices such as microcomputers, memories, gate arrays and the like are integrated into various electrical products such as personal computers, workstations and the like. Most semiconductor devices have input/output (I/O) pins for transmitting data externally, and output circuits such as an output buffer and driver circuit for outputting the internal data externally. When the semiconductor devices are integrated within the electrical products, the I/O pins are connected to transmission lines such as printed wiring on a substrate. Accordingly, the internal data of a semiconductor device is transmitted to another semiconductor device through the transmission line as an interface. In this case, the output impedance of the I/O pin and the impedance of the transmission line must be matched in order for the output data of the semiconductor device to be transmitted through the transmission line.
As the operational speed in the electrical products is improved, the signal swing at the interface between the semiconductor devices needs to be reduced. This is because a short signal swing minimizes transmitting delay time.
However, while the swing width is reduced, the external noise is increased, and the reflection of the output signal becomes critical responsive to an impedance mismatch in an interface terminal. The impedance mismatch may result from external noise, variances in voltage, operational temperature or manufacturing process, and the like. The impedance mismatch might cause difficulties in transmitting high speed data, and result in data skewing at a data output terminal of a semiconductor device.
In a case where the semiconductor device receives the skewed output signal at an input terminal, a set-up/hold failure or min detection in an input level may be caused. A semiconductor memory device having the variable impedance control shown in FIG. 1 in order to perform impedance matching between external semiconductor devices. For example, in the case of HSTL (High Speed Transceiver Logic) interface, one extra pin is used within about several tens of ohm (.OMEGA.) to keep the desired output impedance value. However, the semiconductor memory device adapted for such an impedance matching method cannot frequently obtain the desired output impedance value due to variances in power voltage, operational temperature, process and the like. To solve such a problem, the conventional semiconductor device is provided with a control part having a metal option, bonding option, or fuse option. The control part is used in controlling the scope of resistance value or the reference level for impedance matching. Therefore, such conventional techniques require many hours in test, and also need a separate process for controlling consequently increasing manufacturing costs.
Accordingly, a supplemental technique is required to perform desired impedance matching irrespective of variances in power voltage, operational temperature and manufacturing process.